Abstract: In order to solve the time-consuming and complicated operation problems in convolutional neural networks, this paper proposes a block-based pipeline acceleration method according to the parallelism characteristics of convolution operation, and designs the circuit on System Generator based on this method. Through the experimental verification on field-programmable gate array (FPGA), the design model can correctly output the convolution operation results. In the case of the same structure and input data, the design model can accelerate up to 258 times compared with ordinary CPU in calculation speed, and increase by nearly 40 times compared with server-level CPU, and has a good acceleration effect.